[PATCH] D40145: [RISCV] Fix 64-bit data layout mismatch between backend and target description

[Mandeep Singh Grang via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL318454: [RISCV] Fix 64-bit data layout mismatch between backend and target description (authored by mgrang).

Changed prior to commit:
  https://reviews.llvm.org/D40145?vs=123230&id=123232#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D40145

Files:
  llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp


Index: llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -30,7 +30,7 @@
 
 static std::string computeDataLayout(const Triple &TT) {
   if (TT.isArch64Bit()) {
-    return "e-m:e-i64:64-n32:64-S128";
+    return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
   } else {
     assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
     return "e-m:e-p:32:32-i64:64-n32-S128";


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D40145.123232.patch
Type: text/x-patch
Size: 571 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171116/d842440f/attachment.bin>