[PATCH] D39051: [X86][F16C] Update instruction scheduling on btver2
Andrew V. Tischenko via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 19 04:31:51 PDT 2017
avt77 updated this revision to Diff 119565.
avt77 added a comment.
I fixed issues raised by Simon
https://reviews.llvm.org/D39051
Files:
lib/Target/X86/X86ScheduleBtVer2.td
test/CodeGen/X86/f16c-schedule.ll
Index: test/CodeGen/X86/f16c-schedule.ll
===================================================================
--- test/CodeGen/X86/f16c-schedule.ll
+++ test/CodeGen/X86/f16c-schedule.ll
@@ -45,7 +45,7 @@
;
; BTVER2-LABEL: test_vcvtph2ps_128:
; BTVER2: # BB#0:
-; BTVER2-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [8:1.00]
+; BTVER2-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [3:1.00]
; BTVER2-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
@@ -102,8 +102,8 @@
;
; BTVER2-LABEL: test_vcvtph2ps_256:
; BTVER2: # BB#0:
-; BTVER2-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [8:1.00]
-; BTVER2-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [3:1.00]
+; BTVER2-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [10:2.00]
+; BTVER2-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [5:2.00]
; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -155,7 +155,7 @@
; BTVER2-LABEL: test_vcvtps2ph_128:
; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [8:1.00]
+; BTVER2-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_vcvtps2ph_128:
@@ -209,8 +209,8 @@
;
; BTVER2-LABEL: test_vcvtps2ph_256:
; BTVER2: # BB#0:
-; BTVER2-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [8:1.00]
+; BTVER2-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [6:2.00]
+; BTVER2-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [11:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_vcvtps2ph_256:
Index: lib/Target/X86/X86ScheduleBtVer2.td
===================================================================
--- lib/Target/X86/X86ScheduleBtVer2.td
+++ lib/Target/X86/X86ScheduleBtVer2.td
@@ -387,6 +387,51 @@
def : InstRW<[WriteINSERTQ], (instregex "INSERTQ")>;
////////////////////////////////////////////////////////////////////////////////
+// F16C instructions.
+////////////////////////////////////////////////////////////////////////////////
+
+def WriteCVT3: SchedWriteRes<[JFPU1]> {
+ let Latency = 3;
+}
+def : InstRW<[WriteCVT3], (instregex "VCVTPS2PHrr")>;
+def : InstRW<[WriteCVT3], (instregex "VCVTPH2PSrr")>;
+
+def WriteCVT3St: SchedWriteRes<[JFPU1, JLAGU]> {
+ let Latency = 3;
+ let ResourceCycles = [1, 1];
+}
+def : InstRW<[WriteCVT3St], (instregex "VCVTPS2PHmr")>;
+def : InstRW<[WriteCVT3St], (instregex "VCVTPH2PSrm")>;
+
+def WriteCVTPS2PHY: SchedWriteRes<[JFPU1, JFPU01]> {
+ let Latency = 6;
+ let ResourceCycles = [2,2];
+ let NumMicroOps = 3;
+}
+def : InstRW<[WriteCVTPS2PHY], (instregex "VCVTPS2PHYrr")>;
+
+def WriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JLAGU]> {
+ let Latency = 11;
+ let ResourceCycles = [2,2,1];
+ let NumMicroOps = 3;
+}
+def : InstRW<[WriteCVTPS2PHYSt], (instregex "VCVTPS2PHYmr")>;
+
+def WriteCVTPH2PSY: SchedWriteRes<[JFPU1]> {
+ let Latency = 5;
+ let ResourceCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[WriteCVTPH2PSY], (instregex "VCVTPH2PSYrr")>;
+
+def WriteCVTPH2PSYLd: SchedWriteRes<[JLAGU, JFPU1]> {
+ let Latency = 10;
+ let ResourceCycles = [1,2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[WriteCVTPH2PSYLd], (instregex "VCVTPH2PSYrm")>;
+
+////////////////////////////////////////////////////////////////////////////////
// AVX instructions.
////////////////////////////////////////////////////////////////////////////////
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