[PATCH] D39051: [X86][F16C] Update instruction scheduling on btver2

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

These latencies/throughputs still don't match the AMD docs - please match those and not the Agner tests



================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:404
+def : InstRW<[WriteCVT3St], (instregex "VCVTPS2PHmr")>;
+def : InstRW<[WriteCVT3St], (instregex "VCVTPH2PSrm")>;
+
----------------
VCVTPH2PSrm is a load not a store it can't use WriteCVT3St


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:421
+def WriteCVTPH2PSY: SchedWriteRes<[JFPU1]> {
+  let Latency = 5;
+  let ResourceCycles = [2];
----------------
3


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:428
+def WriteCVTPH2PSYLd: SchedWriteRes<[JLAGU, JFPU1]> {
+  let Latency = 10;
+  let ResourceCycles = [1,2];
----------------
3 + 5 = 8


https://reviews.llvm.org/D39051