[PATCH] D39051: [X86][F16C] Update instruction scheduling on btver2

[Andrew V. Tischenko via Phabricator via llvm-commits]

avt77 added inline comments.


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:405
+
+def WriteCVTPS2PHY: SchedWriteRes<[JFPU0, JFPU1]> {
+  let Latency = 6;
----------------
RKSimon wrote:
> Shouldn't the JFPU1 case be JFPU01? The amd docs say 'STC,FPA|FPM'
It's again a difference between Agner and AMD docs :-(


https://reviews.llvm.org/D39051