[PATCH] D38607: [AMDGPU] New 64 bit div/rem expansion

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 5 19:05:55 PDT 2017


rampitec added inline comments.


================
Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:1623
+
+    // if C3 != 0 ...
+    SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
----------------
b-sumner wrote:
> It wouldn't hurt to have more comments expressing the algorithm in a C-like style.
This is more like todo: we can insert this "if" here and split the BB. That is questionable though if it is profitable in the divergent control flow and not really easy during the lowering. It is substituted by the cndmask after endif comments. Anyway, comment is left if later we decide to use if/then here.


https://reviews.llvm.org/D38607





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