[PATCH] D38181: [x86] swap order of srl (and X, C1), C2 when it saves size

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:31785
+  // If the mask fits in a byte, then we know we can generate smaller and
+  // potentially better code by shifting first.
+  APInt MaskVal = AndC->getAPIntValue();
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What about a larger than 32-bit and mask that would allow us to use a 32-bit and? Otherwise we use a movabsq to load the immediate.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:31837
   if (N->getOpcode() == ISD::SRA)
     if (SDValue V = combineShiftRightAlgebraic(N, DAG))
       return V;
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Not related to this patch, but shouldn't that be "Arithmetic" not "Algebraic"?


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Comment at: test/CodeGen/X86/urem-i8-constant.ll:10
 ; CHECK-NEXT:    shrl $12, %eax
+; CHECK-NEXT:    movzwl %ax, %eax
 ; CHECK-NEXT:    movb $37, %dl
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It's not immediately obvious to me how moving 0x7000 right by 12 bits turned into a mozwl.


https://reviews.llvm.org/D38181