[PATCH] D38181: [x86] swap order of srl (and X, C1), C2 when it saves size

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
Herald added a subscriber: mcrosier.

The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. There are also better improvements based on known-bits that allow us to eliminate the mask entirely.

As noted, this could be extended. There are potentially other wins from always shifting first, but doing that reveals a tangle of problems in other pattern matching. We do this transform generically in instcombine, but we often have icmp IR that doesn't match that pattern.


https://reviews.llvm.org/D38181

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll
  test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
  test/CodeGen/X86/divide-by-constant.ll
  test/CodeGen/X86/known-bits.ll
  test/CodeGen/X86/live-out-reg-info.ll
  test/CodeGen/X86/test-shrink.ll
  test/CodeGen/X86/urem-i8-constant.ll
  test/CodeGen/X86/xor-icmp.ll

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