[PATCH] D38181: [x86] swap order of srl (and X, C1), C2 when it saves size

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: test/CodeGen/X86/urem-i8-constant.ll:10
 ; CHECK-NEXT:    shrl $12, %eax
+; CHECK-NEXT:    movzwl %ax, %eax
 ; CHECK-NEXT:    movb $37, %dl
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craig.topper wrote:
> It's not immediately obvious to me how moving 0x7000 right by 12 bits turned into a mozwl.
Oh there's magic in SelectionDAGISel::CheckAndMask that I never knew about.


https://reviews.llvm.org/D38181