[PATCH] D35010: [IRCE] Recognize loops with ne/eq latch conditions

[Max Kazantsev via Phabricator via llvm-commits]

mkazantsev planned changes to this revision.
mkazantsev added a comment.

Seems that the patch has a bug, needs rework.



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Comment at: lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp:810
+    if (Pred == ICmpInst::ICMP_NE && LatchBrExitIdx == 1)
+      // while (++i != len) {         while (++i < len) {
+      //   ...                 --->     ...
----------------
sanjoy wrote:
> I don't think this equivalence holds if the RHS is negative.
What's the problem with negative RHS? There is no conceptual difference between
  while (++i != 5) ---> while (++i < 5)
and
  while (++i != -5) ---> while (++i < -5)
Maybe what you meant was "if the RHS is less than the IV's initial value"? Such loops get rejected earlier, test_02 exercises this situation. Will add an assert on that.


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Comment at: lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp:850
       IRBuilder<> B(Preheader->getTerminator());
       RightValue = B.CreateAdd(RightValue, One);
     } else {
----------------
Bug here: if we have reduced RightSCEV by one on line 822, we should not increase RightValue by 1.


================
Comment at: lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp:901
       IRBuilder<> B(Preheader->getTerminator());
       RightValue = B.CreateSub(RightValue, One);
     } else {
----------------
Same here.


https://reviews.llvm.org/D35010