[PATCH] D34815: [Power9] Spill gprs to vector registers rather than stack

[Zaara Syeda via Phabricator via llvm-commits]

syzaara added inline comments.


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Comment at: test/CodeGen/PowerPC/gpr-vsr-spill2.ll:25
+define void @search_root(%struct.move_s* noalias nocapture sret %agg.result, i32 signext %originalalpha, i32 signext %originalbeta, i32 signext %depth) {
+; CHECK:        mr [[NEWREG:[0-9]+]], {{[0-9]+}}
+; CHECK:        std [[NEWREG]], {{[0-9]+}}(1)                   # 8-byte Folded Spill
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inouehrs wrote:
> What's the intention of this complicated test case without spills to VSR?
This case shows how a spill of the new reg class is handled. Here we spilled a GPR to GPFPR where the new reg was also a gpr. We then needed to spill the new GPFPR using either a scalar store or vector store depending on the allocated register.


https://reviews.llvm.org/D34815