[PATCH] D33866: [DAGCombiner] loosen restriction for creating narrow vector load from extract(wide load)

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 101415.
spatel added a comment.

Patch updated:
Rebased after https://reviews.llvm.org/rL304718 - the AVX1 non-temporal isel got fixed there, so now we just see different scheduling in those tests.


https://reviews.llvm.org/D33866

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/arm64-vabs.ll
  test/CodeGen/AArch64/merge-store.ll
  test/CodeGen/ARM/combine-vmovdrr.ll
  test/CodeGen/ARM/vext.ll
  test/CodeGen/ARM/vpadd.ll
  test/CodeGen/ARM/vzip.ll
  test/CodeGen/X86/avx-vperm2x128.ll
  test/CodeGen/X86/avx-vzeroupper.ll
  test/CodeGen/X86/avx512-cvt.ll
  test/CodeGen/X86/nontemporal-loads.ll
  test/CodeGen/X86/oddshuffles.ll
  test/CodeGen/X86/pr22774.ll
  test/CodeGen/X86/sandybridge-loads.ll
  test/CodeGen/X86/shuffle-vs-trunc-256.ll
  test/CodeGen/X86/shuffle-vs-trunc-512.ll
  test/CodeGen/X86/subvector-broadcast.ll
  test/CodeGen/X86/vec_int_to_fp.ll
  test/CodeGen/X86/vector-compare-results.ll
  test/CodeGen/X86/vector-shift-ashr-256.ll
  test/CodeGen/X86/vector-shift-lshr-256.ll
  test/CodeGen/X86/vector-shift-shl-256.ll
  test/CodeGen/X86/viabs.ll
  test/CodeGen/X86/x86-interleaved-access.ll

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