[PATCH] D33866: [DAGCombiner] loosen restriction for creating narrow vector load from extract(wide load)

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 101412.
spatel edited the summary of this revision.
spatel added a reviewer: t.p.northover.
spatel added a comment.

Patch updated:

1. Remove the one-use restriction.
2. Add the TLI..shouldReduceLoadWidth() predicate.

So now we see the full effect on x86, sidestep the AMDGPU problems, but seem to have introduced some ARM regressions.

AFAICT, the x86 diffs are all wins. This includes an improvement to select non-temporal loads where we failed to do so before.


https://reviews.llvm.org/D33866

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/arm64-vabs.ll
  test/CodeGen/AArch64/merge-store.ll
  test/CodeGen/ARM/combine-vmovdrr.ll
  test/CodeGen/ARM/vext.ll
  test/CodeGen/ARM/vpadd.ll
  test/CodeGen/ARM/vzip.ll
  test/CodeGen/X86/avx-vperm2x128.ll
  test/CodeGen/X86/avx-vzeroupper.ll
  test/CodeGen/X86/avx512-cvt.ll
  test/CodeGen/X86/nontemporal-loads.ll
  test/CodeGen/X86/oddshuffles.ll
  test/CodeGen/X86/pr22774.ll
  test/CodeGen/X86/sandybridge-loads.ll
  test/CodeGen/X86/shuffle-vs-trunc-256.ll
  test/CodeGen/X86/shuffle-vs-trunc-512.ll
  test/CodeGen/X86/subvector-broadcast.ll
  test/CodeGen/X86/vec_int_to_fp.ll
  test/CodeGen/X86/vector-compare-results.ll
  test/CodeGen/X86/vector-shift-ashr-256.ll
  test/CodeGen/X86/vector-shift-lshr-256.ll
  test/CodeGen/X86/vector-shift-shl-256.ll
  test/CodeGen/X86/viabs.ll
  test/CodeGen/X86/x86-interleaved-access.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D33866.101412.patch
Type: text/x-patch
Size: 126225 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170605/cc2ce54f/attachment-0001.bin>