[PATCH] D30661: [x86] Split MXCSR into two pseudo-registers

[Andy Kaylor via Phabricator via llvm-commits]

andrew.w.kaylor added a comment.

In https://reviews.llvm.org/D30661#693861, @efriedma wrote:

> It's not just DCE which is problematic... we could also sink a floating-point operation past a read from the status register.  I suppose you could prevent that particular problem by making reads from the status register write to the control bits, but that causes its own problems.


Well, that's exactly the sort of thing I am trying to stop.  I was under the impression that if all FP operations have an implicit def of the status bits that would be sufficient to prevent the from being sunk past a read of the status bits.  Are you saying that if I have two FP operations with defs of 'mxcsr_s' the back end will be free to assume that the first one can sink past the second operation and a subsequent read of the status bits?


Repository:
  rL LLVM

https://reviews.llvm.org/D30661