[PATCH] D30661: [x86] Split MXCSR into two pseudo-registers

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> Well, that's exactly the sort of thing I am trying to stop. I was under the impression that if all FP operations have an implicit def of the status bits that would be sufficient to prevent the from being sunk past a read of the status bits. Are you saying that if I have two FP operations with defs of 'mxcsr_s' the back end will be free to assume that the first one can sink past the second operation and a subsequent read of the status bits?

Yes.  "def" means completely overwriting the old value, so if you have two operations which def a register, the first definition is dead (whether or not the instruction is dead as a whole).  You might want to look at how the x86 backend models arithmetic instructions which set EFLAGS to see how this works in practice; the scheduler will, for example, move an ADD across a CMP+CMOV.


Repository:
  rL LLVM

https://reviews.llvm.org/D30661