[PATCH] D30400: For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes, same as already done for ARM and Thumb2.

[A. Skrobov via Phabricator via llvm-commits]

tyomitch added a comment.

> Why not? "t2ADDSrr" is a pseudo-instruction, not an actual encoding.

Right; but t2ADC / t2SBC are actual encodings (non-predicable, with non-optional def for CPSR), unlike tADC / tSBC (predicable, with an OptionalDef for CPSR).

It might be possible to do a hybrid implementation, using tPseudoInsts for tADDS / tSUBS, and custom C++ lowering for tADC / tSBC; although this feels like, out of two evils, choosing both.
It would also require duplicating a substantial portion of the code in `ARMTargetLowering::AdjustInstrPostInstrSelection` to take care of Thumb1 instructions separately, because their MIs have a different structure: in particular, the cc_out operand that `AdjustInstrPostInstrSelection` is adding must, in Thumb1 instructions, be not last but 1st (and `MachineInstr` doesn't even have an API to insert a new operand into the middle of an existing instruction).



================
Comment at: lib/Target/ARM/ARMISelDAGToDAG.cpp:3318
+          isAdd = !isAdd;
+        }
+        if (imm < 256) {
----------------
efriedma wrote:
> The old patterns don't handle SUBC with an immediate.  You can produce this situation with something like this:
> 
> ```
> long long x(long long a, int b) {
>   return a - (((long long)b << 32) | -1U);
> }
> ```
> 
> I think the handling here is correct, but please change it in a separate patch.  
The old patterns lower this code into:
```
        movs    r3, #0
        mvns    r3, r3
        subs    r0, r0, r3
        sbcs    r1, r2
```
on Thumb1, and into much more compact
```
        subs.w  r0, r0, #-1
        sbcs    r1, r2
```
on Thumb2. The new code lowers it into
```
        adds    r0, r0, #1
        sbcs    r1, r2
```
which is equivalent, and even a bit more compact.
I don't really see what the problem is, either with the old patterns or with the new code.


https://reviews.llvm.org/D30400