[PATCH] D30472: [DAGCombine] Simplify ISD::AND in GetDemandedBits.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D30472#689093, @efriedma wrote:

> I took a brief look, but there isn't any obvious cause.  Maybe some x86 combine interacting badly with the fact that AVX-512 makes i1 a legal type.


No problem - I'm rummaging around down here, so I'll try to find it. I don't think bogus sbb lowering is worth holding up this patch. Once Simon's concern is addressed, this should be good.


Repository:
  rL LLVM

https://reviews.llvm.org/D30472