[PATCH] D30472: [DAGCombine] Simplify ISD::AND in GetDemandedBits.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> How often are cases from each operand occurring? Since we canonicalize constants to the RHS would it be performant to test that first?

The cases affected here are all AND with a constant mask.  Should I special-case constants, or just rearrange order of the checks?

> It's not this patch's fault of course, but that set -> sbb transform looks like a regression for every CPU that I checked in Agner's tables (sbb has higher latency and/or less throughput). Should we fix that first?

I took a brief look, but there isn't any obvious cause.  Maybe some x86 combine interacting badly with the fact that AVX-512 makes i1 a legal type.


Repository:
  rL LLVM

https://reviews.llvm.org/D30472