[PATCH] D30472: [DAGCombine] Simplify ISD::AND in GetDemandedBits.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

It's not this patch's fault of course, but that set -> sbb transform looks like a regression for every CPU that I checked in Agner's tables (sbb has higher latency and/or less throughput). 
Should we fix that first?


Repository:
  rL LLVM

https://reviews.llvm.org/D30472