[PATCH] D27998: [AArch64] Consider all vector types for FeatureSlowMisaligned128Store

[Matthew Simpson via Phabricator via llvm-commits]

mssimpso added a comment.

This makes sense to me, but it's probably a good idea to have someone with Cyclone knowledge comment.



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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:471
   if (ST->isMisaligned128StoreSlow() && Opcode == Instruction::Store &&
-      Src->isVectorTy() && Alignment != 16 &&
-      Src->getVectorElementType()->isIntegerTy(64)) {
-    // Unaligned stores are extremely inefficient. We don't split
-    // unaligned v2i64 stores because the negative impact that has shown in
-    // practice on inlined memcpy code.
-    // We make v2i64 stores expensive so that we will only vectorize if there
+      Src->getPrimitiveSizeInBits() == 128 && Alignment < 16) {
+    // Unaligned stores are extremely inefficient. We don't split all
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Would it make sense to check the legalized type here? Something like LT.second.is128BitVector()?


Repository:
  rL LLVM

https://reviews.llvm.org/D27998