[PATCH] D27998: [AArch64] Consider all vector types for FeatureSlowMisaligned128Store

[Renato Golin via Phabricator via llvm-commits]

rengolin accepted this revision.
rengolin added a reviewer: rengolin.
rengolin added a comment.
This revision is now accepted and ready to land.

This makes sense. LGTM. Thanks!



================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:471
   if (ST->isMisaligned128StoreSlow() && Opcode == Instruction::Store &&
-      Src->isVectorTy() && Alignment != 16 &&
-      Src->getVectorElementType()->isIntegerTy(64)) {
-    // Unaligned stores are extremely inefficient. We don't split
-    // unaligned v2i64 stores because the negative impact that has shown in
-    // practice on inlined memcpy code.
-    // We make v2i64 stores expensive so that we will only vectorize if there
+      Src->getPrimitiveSizeInBits() == 128 && Alignment < 16) {
+    // Unaligned stores are extremely inefficient. We don't split all
----------------
mssimpso wrote:
> Would it make sense to check the legalized type here? Something like LT.second.is128BitVector()?
I'm not sure the type would make any difference on the store. All that matters is that this is a 128-bit store and the required alignment is larger than that. The previous conditional was weird, I think.


Repository:
  rL LLVM

https://reviews.llvm.org/D27998