[PATCH] D27997: [AMDGPU] Prevent spills before exec mask is restored

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked an inline comment as done.
rampitec added inline comments.


================
Comment at: include/llvm/Target/TargetInstrInfo.h:1515
+  /// a good insertion point.
+  virtual bool isPositionLike(const MachineInstr &MI) const {
+    return false;
----------------
rampitec wrote:
> qcolombet wrote:
> > For the comment, I would use the same terminology as MachineInstr::isPosition. Right now, the comment seems off compared to the function name.
> > Also, would it make sense to have this flag exposed in the TDs?
> Fixed comment.
> I thought about exposing the flag in TD, but it is not always can be expressed that way. The same instruction can be used at the end of a basic block, so this in fact does not necessarily depend on the instruction only.
And then instructions themselves are just a scalar or/and/xor etc, they just happen to write exec mask register. If exposed through a bit in TD all of them would need to be duplicated as pseudo and expanded past RA, which is clearly more definitions and more code.


Repository:
  rL LLVM

https://reviews.llvm.org/D27997