[PATCH] D26799: [X86][AVX512] Instructions fixups

[Craig Topper via llvm-commits]

craig.topper added a comment.

That has to be a mistake in the documentation. It seems very unlikely they would have changed the behavior between SSE/AVX and AVX-512. The description under the table in the Intel docs does mention 64-bit memory location.

"EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit
memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand
is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX
embedded rounding is ignored."


Repository:
  rL LLVM

https://reviews.llvm.org/D26799