[llvm] r284088 - [AArch64][RegisterBankInfo] Bump the cost of vector loads.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Wed Oct 12 19:11:59 2016
New Revision: 284088

URL: http://llvm.org/viewvc/llvm-project?rev=284088&view=rev
Log:
[AArch64][RegisterBankInfo] Bump the cost of vector loads.

This does not change anything yet, because we do not offer any
alternative mapping.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=284088&r1=284087&r2=284088&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Wed Oct 12 19:11:59 2016
@@ -431,6 +431,16 @@ AArch64RegisterBankInfo::getInstrMapping
                    *AArch64::PartMappings[OpRegBankIdx[1]].RegBank, OpSize[0]);
     break;
   }
+  case TargetOpcode::G_LOAD: {
+    // Loading in vector unit is slightly more expensive.
+    // This is actually only true for the LD1R and co instructions,
+    // but anyway for the fast mode this number does not matter and
+    // for the greedy mode the cost of the cross bank copy will
+    // offset this number.
+    // FIXME: Should be derived from the scheduling model.
+    if (OpRegBankIdx[0] >= AArch64::FirstFPR)
+      Cost = 2;
+  }
   }
 
   // Finally construct the computed mapping.