[llvm] r284087 - [AArch64][RegisterBankInfo] Use a proper cost for cross regbank G_BITCASTs.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Wed Oct 12 19:11:57 2016
New Revision: 284087

URL: http://llvm.org/viewvc/llvm-project?rev=284087&view=rev
Log:
[AArch64][RegisterBankInfo] Use a proper cost for cross regbank G_BITCASTs.

This does not change anything yet, because we do not offer any
alternative mapping.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=284087&r1=284086&r2=284087&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Wed Oct 12 19:11:57 2016
@@ -383,8 +383,6 @@ AArch64RegisterBankInfo::getInstrMapping
   }
 
   unsigned NumOperands = MI.getNumOperands();
-  RegisterBankInfo::InstructionMapping Mapping =
-      InstructionMapping{DefaultMappingID, 1, nullptr, NumOperands};
 
   // Track the size and bank of each register.  We don't do partial mappings.
   SmallVector<unsigned, 4> OpSize(NumOperands);
@@ -405,6 +403,7 @@ AArch64RegisterBankInfo::getInstrMapping
       OpRegBankIdx[Idx] = AArch64::FirstGPR;
   }
 
+  unsigned Cost = 1;
   // Some of the floating-point instructions have mixed GPR and FPR operands:
   // fine-tune the computed mapping.
   switch (Opc) {
@@ -424,9 +423,19 @@ AArch64RegisterBankInfo::getInstrMapping
                     AArch64::FirstFPR, AArch64::FirstFPR};
     break;
   }
+  case TargetOpcode::G_BITCAST: {
+    // This is going to be a cross register bank copy and this is expensive.
+    if (OpRegBankIdx[0] != OpRegBankIdx[1])
+      Cost =
+          copyCost(*AArch64::PartMappings[OpRegBankIdx[0]].RegBank,
+                   *AArch64::PartMappings[OpRegBankIdx[1]].RegBank, OpSize[0]);
+    break;
+  }
   }
 
   // Finally construct the computed mapping.
+  RegisterBankInfo::InstructionMapping Mapping =
+      InstructionMapping{DefaultMappingID, Cost, nullptr, NumOperands};
   SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx)
     if (MI.getOperand(Idx).isReg())