[llvm] r281738 - [AArch64][GlobalISel] Add default regbank mapping for G_FCMP.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 16 08:12:43 PDT 2016
Author: ab
Date: Fri Sep 16 10:12:43 2016
New Revision: 281738
URL: http://llvm.org/viewvc/llvm-project?rev=281738&view=rev
Log:
[AArch64][GlobalISel] Add default regbank mapping for G_FCMP.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=281738&r1=281737&r2=281738&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Fri Sep 16 10:12:43 2016
@@ -221,6 +221,16 @@ AArch64RegisterBankInfo::getInstrMapping
OpBanks[Idx] = AArch64::GPRRegBankID;
}
+ // Some of the floating-point instructions have mixed GPR and FPR operands:
+ // fine-tune the computed mapping.
+ switch (Opc) {
+ case TargetOpcode::G_FCMP: {
+ OpBanks = {AArch64::GPRRegBankID, /* Predicate */ 0, AArch64::FPRRegBankID,
+ AArch64::FPRRegBankID};
+ break;
+ }
+ }
+
// Finally construct the computed mapping.
for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx)
if (MI.getOperand(Idx).isReg())
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir?rev=281738&r1=281737&r2=281738&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir Fri Sep 16 10:12:43 2016
@@ -59,6 +59,8 @@
define void @test_fconstant_s32() { ret void }
+ define void @test_fcmp_s32() { ret void }
+
...
---
@@ -766,3 +768,22 @@ body: |
; CHECK: %0(s32) = G_FCONSTANT float 1.0
%0(s32) = G_FCONSTANT float 1.0
...
+
+---
+# CHECK-LABEL: name: test_fcmp_s32
+name: test_fcmp_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %s0
+ ; CHECK: %0(s32) = COPY %s0
+ ; CHECK: %1(s1) = G_FCMP floatpred(olt), %0(s32), %0
+ %0(s32) = COPY %s0
+ %1(s1) = G_FCMP floatpred(olt), %0, %0
+...
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