[llvm] r281739 - [AArch64][GlobalISel] Add default regbank mapping for int<>FP.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 16 08:12:46 PDT 2016
Author: ab
Date: Fri Sep 16 10:12:46 2016
New Revision: 281739
URL: http://llvm.org/viewvc/llvm-project?rev=281739&view=rev
Log:
[AArch64][GlobalISel] Add default regbank mapping for int<>FP.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=281739&r1=281738&r2=281739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Fri Sep 16 10:12:46 2016
@@ -224,6 +224,16 @@ AArch64RegisterBankInfo::getInstrMapping
// Some of the floating-point instructions have mixed GPR and FPR operands:
// fine-tune the computed mapping.
switch (Opc) {
+ case TargetOpcode::G_SITOFP:
+ case TargetOpcode::G_UITOFP: {
+ OpBanks = {AArch64::FPRRegBankID, AArch64::GPRRegBankID};
+ break;
+ }
+ case TargetOpcode::G_FPTOSI:
+ case TargetOpcode::G_FPTOUI: {
+ OpBanks = {AArch64::GPRRegBankID, AArch64::FPRRegBankID};
+ break;
+ }
case TargetOpcode::G_FCMP: {
OpBanks = {AArch64::GPRRegBankID, /* Predicate */ 0, AArch64::FPRRegBankID,
AArch64::FPRRegBankID};
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir?rev=281739&r1=281738&r2=281739&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir Fri Sep 16 10:12:46 2016
@@ -61,6 +61,11 @@
define void @test_fcmp_s32() { ret void }
+ define void @test_sitofp_s64_s32() { ret void }
+ define void @test_uitofp_s32_s64() { ret void }
+
+ define void @test_fptosi_s64_s32() { ret void }
+ define void @test_fptoui_s32_s64() { ret void }
...
---
@@ -787,3 +792,79 @@ body: |
%0(s32) = COPY %s0
%1(s1) = G_FCMP floatpred(olt), %0, %0
...
+
+---
+# CHECK-LABEL: name: test_sitofp_s64_s32
+name: test_sitofp_s64_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %w0
+ ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: %1(s64) = G_SITOFP %0
+ %0(s32) = COPY %w0
+ %1(s64) = G_SITOFP %0
+...
+
+---
+# CHECK-LABEL: name: test_uitofp_s32_s64
+name: test_uitofp_s32_s64
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: gpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %x0
+ ; CHECK: %0(s64) = COPY %x0
+ ; CHECK: %1(s32) = G_UITOFP %0
+ %0(s64) = COPY %x0
+ %1(s32) = G_UITOFP %0
+...
+
+---
+# CHECK-LABEL: name: test_fptosi_s64_s32
+name: test_fptosi_s64_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %s0
+ ; CHECK: %0(s32) = COPY %s0
+ ; CHECK: %1(s64) = G_FPTOSI %0
+ %0(s32) = COPY %s0
+ %1(s64) = G_FPTOSI %0
+...
+
+---
+# CHECK-LABEL: name: test_fptoui_s32_s64
+name: test_fptoui_s32_s64
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: gpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %d0
+ ; CHECK: %0(s64) = COPY %d0
+ ; CHECK: %1(s32) = G_FPTOUI %0
+ %0(s64) = COPY %d0
+ %1(s32) = G_FPTOUI %0
+...
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