[llvm] r281737 - [AArch64][GlobalISel] Add default regbank mapping for FP ops.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 16 08:12:40 PDT 2016
Author: ab
Date: Fri Sep 16 10:12:40 2016
New Revision: 281737
URL: http://llvm.org/viewvc/llvm-project?rev=281737&view=rev
Log:
[AArch64][GlobalISel] Add default regbank mapping for FP ops.
These should have all their operands - even scalars - go on FPR.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=281737&r1=281736&r2=281737&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Fri Sep 16 10:12:40 2016
@@ -169,6 +169,22 @@ void AArch64RegisterBankInfo::applyMappi
}
}
+/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
+/// having only floating-point operands.
+static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
+ switch (Opc) {
+ case TargetOpcode::G_FADD:
+ case TargetOpcode::G_FSUB:
+ case TargetOpcode::G_FMUL:
+ case TargetOpcode::G_FDIV:
+ case TargetOpcode::G_FCONSTANT:
+ case TargetOpcode::G_FPEXT:
+ case TargetOpcode::G_FPTRUNC:
+ return true;
+ }
+ return false;
+}
+
RegisterBankInfo::InstructionMapping
AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
const unsigned Opc = MI.getOpcode();
@@ -198,7 +214,8 @@ AArch64RegisterBankInfo::getInstrMapping
OpSizes[Idx] = Ty.getSizeInBits();
// As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
- if (Ty.isVector())
+ // For floating-point instructions, scalars go in FPRs.
+ if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
OpBanks[Idx] = AArch64::FPRRegBankID;
else
OpBanks[Idx] = AArch64::GPRRegBankID;
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir?rev=281737&r1=281736&r2=281737&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir Fri Sep 16 10:12:40 2016
@@ -48,6 +48,17 @@
define void @test_load_s32_p0() { ret void }
define void @test_store_s32_p0() { ret void }
+
+ define void @test_fadd_s32() { ret void }
+ define void @test_fsub_s32() { ret void }
+ define void @test_fmul_s32() { ret void }
+ define void @test_fdiv_s32() { ret void }
+
+ define void @test_fpext_s64_s32() { ret void }
+ define void @test_fptrunc_s32_s64() { ret void }
+
+ define void @test_fconstant_s32() { ret void }
+
...
---
@@ -627,3 +638,131 @@ body: |
%1(s32) = COPY %w1
G_STORE %1, %0
...
+
+---
+# CHECK-LABEL: name: test_fadd_s32
+name: test_fadd_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %s0
+ ; CHECK: %0(s32) = COPY %s0
+ ; CHECK: %1(s32) = G_FADD %0, %0
+ %0(s32) = COPY %s0
+ %1(s32) = G_FADD %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_fsub_s32
+name: test_fsub_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %s0
+ ; CHECK: %0(s32) = COPY %s0
+ ; CHECK: %1(s32) = G_FSUB %0, %0
+ %0(s32) = COPY %s0
+ %1(s32) = G_FSUB %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_fmul_s32
+name: test_fmul_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %s0
+ ; CHECK: %0(s32) = COPY %s0
+ ; CHECK: %1(s32) = G_FMUL %0, %0
+ %0(s32) = COPY %s0
+ %1(s32) = G_FMUL %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_fdiv_s32
+name: test_fdiv_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %s0
+ ; CHECK: %0(s32) = COPY %s0
+ ; CHECK: %1(s32) = G_FDIV %0, %0
+ %0(s32) = COPY %s0
+ %1(s32) = G_FDIV %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_fpext_s64_s32
+name: test_fpext_s64_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %s0
+ ; CHECK: %0(s32) = COPY %s0
+ ; CHECK: %1(s64) = G_FPEXT %0
+ %0(s32) = COPY %s0
+ %1(s64) = G_FPEXT %0
+...
+
+---
+# CHECK-LABEL: name: test_fptrunc_s32_s64
+name: test_fptrunc_s32_s64
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+# CHECK: - { id: 1, class: fpr }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %d0
+ ; CHECK: %0(s64) = COPY %d0
+ ; CHECK: %1(s32) = G_FPTRUNC %0
+ %0(s64) = COPY %d0
+ %1(s32) = G_FPTRUNC %0
+...
+
+---
+# CHECK-LABEL: name: test_fconstant_s32
+name: test_fconstant_s32
+legalized: true
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr }
+registers:
+ - { id: 0, class: _ }
+body: |
+ bb.0:
+ ; CHECK: %0(s32) = G_FCONSTANT float 1.0
+ %0(s32) = G_FCONSTANT float 1.0
+...
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