[PATCH] D23561: [RISCV 4/10] Add basic RISCV{InstrFormats, InstrInfo, RegisterInfo, }.td

[David Chisnall via llvm-commits]

theraven added a comment.

Comments inline.


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Comment at: lib/Target/RISCV/RISCV.td:23
@@ +22,3 @@
+
+def : ProcessorModel<"RV64I", NoSchedModel, [Feature64Bit]>;
+
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Should these not be `Processor`, rather than `ProcessorModel`.  I was under the impression that `Processor` is intended for generic families, whereas `ProcessorModel` was intended for specific microarchitectures.

It would be nice to have Rocket as a specific `ProcessorModel` here.  It may be in a later review, but we should probably also have `SubtargetFeature` flags for floating point, atomics, and so on here too.


https://reviews.llvm.org/D23561