[PATCH] D15515: [AArch64] Add DAG combine for extract extend pattern

[Matthew Simpson via llvm-commits]

mssimpso updated this revision to Diff 43010.
mssimpso added a comment.

Added additional type checking noted by James.


http://reviews.llvm.org/D15515

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/arm64-neon-copy.ll

Index: test/CodeGen/AArch64/arm64-neon-copy.ll
===================================================================
--- test/CodeGen/AArch64/arm64-neon-copy.ll
+++ test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -320,21 +320,20 @@
   ret i32 %tmp5
 }
 
-define i32 @smovx16b(<16 x i8> %tmp1) {
+define i64 @smovx16b(<16 x i8> %tmp1) {
 ; CHECK-LABEL: smovx16b:
-; CHECK: smov {{[xw][0-9]+}}, {{v[0-9]+}}.b[8]
+; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[8]
   %tmp3 = extractelement <16 x i8> %tmp1, i32 8
-  %tmp4 = sext i8 %tmp3 to i32
-  %tmp5 = add i32 %tmp4, %tmp4
-  ret i32 %tmp5
+  %tmp4 = sext i8 %tmp3 to i64
+  ret i64 %tmp4
 }
 
-define i32 @smovx8h(<8 x i16> %tmp1) {
+define i64 @smovx8h(<8 x i16> %tmp1) {
 ; CHECK-LABEL: smovx8h:
-; CHECK: smov {{[xw][0-9]+}}, {{v[0-9]+}}.h[2]
+; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <8 x i16> %tmp1, i32 2
-  %tmp4 = sext i16 %tmp3 to i32
-  ret i32 %tmp4
+  %tmp4 = sext i16 %tmp3 to i64
+  ret i64 %tmp4
 }
 
 define i64 @smovx4s(<4 x i32> %tmp1) {
Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8437,6 +8437,24 @@
     }
   }
 
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+
+  // If we see (any_extend (extract_vector_element v, i)), we can potentially
+  // remove the extend and promote the extract. We can do this if the vector
+  // type is legal and if the result is sign extended from the element type.
+  if (DCI.isAfterLegalizeVectorOps() && N->getOpcode() == ISD::ANY_EXTEND &&
+      N->hasOneUse() && N->use_begin()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+    const SDValue &N0 = N->getOperand(0);
+    EVT DstTy = N->getValueType(0);
+    EVT SrcTy = cast<VTSDNode>(N->use_begin()->getOperand(1))->getVT();
+    EVT VecTy = N0.getOperand(0).getValueType();
+    EVT ElmTy = VecTy.getScalarType();
+    if (N0.getNode()->hasOneUse() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT)
+      if (TLI.isTypeLegal(VecTy) && SrcTy == ElmTy)
+        return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), DstTy,
+                           N0.getOperand(0), N0.getOperand(1));
+  }
+
   // This is effectively a custom type legalization for AArch64.
   //
   // Type legalization will split an extend of a small, legal, type to a larger
@@ -8467,7 +8485,6 @@
   // We're only interested in cleaning things up for non-legal vector types
   // here. If both the source and destination are legal, things will just
   // work naturally without any fiddling.
-  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   EVT ResVT = N->getValueType(0);
   if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
     return SDValue();


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