[PATCH] D15515: [AArch64] Add DAG combine for extract extend pattern

[Matthew Simpson via llvm-commits]

mssimpso marked an inline comment as done.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8444
@@ +8443,3 @@
+  // remove the extend and promote the extract. We can do this if the vector
+  // type is legal and if the result is sign extended from the element type.
+  if (DCI.isAfterLegalizeVectorOps() && N->getOpcode() == ISD::ANY_EXTEND &&
----------------
James,

You're right. Thanks for joining the review! We also need to check that the vector element type is the same as the type we're sign extending from.

Yes, this combine is intended to canonicalize the patterns we match to SMOV. The existing patterns attempt match (sext_inreg (vector_extract v, i)) for the legal types. However, the 16xi8-to-i64 case and the 8xi16-to-i64 case (which we have patterns for) don't actually follow this form because there is an added any_extend. An any_extend from i32 to i64 is added by the type legalizer because it legalizes the extracted elements to i32. So for example, for the case below:

```
define i64 @f(<16 x i8> %a) {
entry:
  %e = extractelement <16 x i8> %a, i32 2
  %b = zext i8 %e to i64
  ret i64 %b
}
```

we currently generate:

```
umov	w8, v0.b[2]
sxtb	x0, w8
```

With this DAG combine, we will instead generate the following code because the existing 16xi8-to-i64 pattern will fire.

```
smov	x0, v0.b[2]
```


http://reviews.llvm.org/D15515