[PATCH] D15515: [AArch64] Add DAG combine for extract extend pattern

[James Molloy via llvm-commits]

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8444
@@ +8443,3 @@
+  // remove the extend and promote the extract. We can do this if the vector
+  // type is legal and if we know the result is sign extended.
+  if (DCI.isAfterLegalizeVectorOps() && N->getOpcode() == ISD::ANY_EXTEND &&
----------------
I suppose we need the sign extend because ISD::EXTRACT_VECTOR_ELT gets matched to "smov"? Perhaps that's something that needs changing - surely we should match (sign_ext_inreg (extract_vector_elt)) to smov and (zero_ext_inreg (extract_vector_elt)) to umov.

I think there needs to be more type checking going on here. Consider:

  %0 = EXTRACT_VECTOR_ELT <8 x i16> %a  ; %0 is i16
  %1 = ANYEXT i16 %0 to i32 ; %1 is i32
  %2 = SIGN_EXTEND_INREG i32 %0 (from i8 to i32) ; bit[7] is replicated into bit[8..31]

This cannot be an SMOVv8i16, because the sign bit is bit[7], not bit[15]. This testcase shows it:

  define i64 @matt(<8 x i16> %a) {
    %b = extractelement <8 x i16> %a, i32 1
    %c = trunc i16 %b to i8
    %d = sext i8 %c to i64
    ret i64 %d
  }

  SelectionDAG has 11 nodes:
  t0: ch = EntryToken
          t2: v8i16,ch = CopyFromReg t0, Register:v8i16 %vreg0
        t14: i32 = extract_vector_elt t2, Constant:i64<1>
      t15: i64 = any_extend t14
    t13: i64 = sign_extend_inreg t15, ValueType:ch:i8
  t9: ch,glue = CopyToReg t0, Register:i64 %X0, t13
  t10: ch = AArch64ISD::RET_FLAG t9, Register:i64 %X0, t9:1


http://reviews.llvm.org/D15515