[PATCH] D14900: [mips] SelectionDAGISel subclasses now follow the optimization level.

[Paul Robinson via llvm-commits]

probinson added a comment.

In http://reviews.llvm.org/D14900#295024, @vradosavljevic wrote:

> In http://reviews.llvm.org/D14900#294537, @dsanders wrote:
>
> > I'm not sure what to do about the test. I've preserved what it was really testing for now but I believe the intention was to test SelectionDAG and not FastISel. Unfortunately, reverting the original change that added this test (http://reviews.llvm.org/rL237153) does not change the output of SelectionDAG.
> >
> > Added the author and commit-er for their opinion.
>
>
> In this test we're checking that register scavenging spill slot is close to $fp, but this commit (http://reviews.llvm.org/rL238829) changed the essence of this test. Any reason why this happened?


The test looks likes it's trying to create enough register pressure to induce the use of the "scavenging spill slot," but that would depend on exactly what the DAG looks like and which register allocator pass you're using.  The -O0/-O2 confusion, -fast-isel=false, and 'optnone' tweaks all seem to be attempts to set up exactly the right conditions.  Is there a way to control pass selection more directly?


http://reviews.llvm.org/D14900