[PATCH] D14900: [mips] SelectionDAGISel subclasses now follow the optimization level.

[Daniel Sanders via llvm-commits]

dsanders added a comment.

> In this test we're checking that register scavenging spill slot is close to $fp, but this commit (http://reviews.llvm.org/rL238829) changed the essence of this test. Any reason why this happened?


The main aim of r238829 was to correctly align vector locals on the stack since (in the O32 ABI) the maximum alignment is 8 and vectors need 16*. The test uses a few vectors so that explains why it was affected, however dynamic stack realignment reserves an additional register so I'd have thought it would make triggering the register scavenger more likely. I'll take a closer look.

*Actually, they only need element-size alignment but I don't think we can describe that and we should get better performance from 16 anyway.


http://reviews.llvm.org/D14900