[PATCH] D14489: [AArch64] Applying load pair optimization for volatile load/store

[Tim Northover via llvm-commits]

t.p.northover added a comment.

> It still unclear to me that ldp/stp preserve ordering between the loads/stores.


I think the principle is sound, but we need to be very careful about what gets combined (for example I don't think we could extend the "strb wzr;strb wzr -> strh wzr" optimisation to volatiles). I think the key point in the ARM ARM is how the access is written for LDP/STP:

  Mem[address + 0, dbytes, acctype] = data1;
  Mem[address + dbytes, dbytes, acctype] = data2;

That seems to me exactly what you'd write for an operation that did guarantee it would preserve the memory characteristics of the split operations.

> If the ordering isn't preserved, we might be able to get away with reordering volatiles in practice, but I can't imagine this would be the case for atomics.


I don't think you can get away with reordering volatiles at all. Their defining property is that the order is preserved, and they are one of the directly observable facets of C's abstract machine.

Atomics, less so (at least memory_order_relaxed ones); you might even be able to reorder seq_cst ones with a sophisticated enough application of the "as-if" rule, though the backend would never do that.


http://reviews.llvm.org/D14489