[PATCH] D14489: [AArch64] Applying load pair optimization for volatile load/store

[Chad Rosier via llvm-commits]

mcrosier added a comment.

After a bit of digging I'm fairly concerned this isn't a valid optimization.  The hasOrderedMemoryRef not only models volatiles, but it also models atomics.

It still unclear to me that ldp/stp preserve ordering between the loads/stores.  If the ordering isn't preserved, we might be able to get away with reordering volatiles in practice, but I can't imagine this would be the case for atomics.

Does anyone agree/disagree?  I'm also wondering if the risk is worth the reward.


http://reviews.llvm.org/D14489