[PATCH] D14534: [AArch64] Fix halfword load merging for big-endian targets

[Renato Golin via llvm-commits]

rengolin accepted this revision.
rengolin added a reviewer: rengolin.
rengolin added a comment.
This revision is now accepted and ready to land.

If the answer to my question is "yes", LGTM. If not, an assert somewhere would fix it. Thanks!


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Comment at: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:568
@@ -562,3 +567,3 @@
     MachineInstr *ExtDestMI = MergeForward ? Paired : I;
-    if (ExtDestMI == Rt2MI) {
+    if ((ExtDestMI == Rt2MI) == Subtarget->isLittleEndian()) {
       // Create the bitfield extract for high half.
----------------
I'm guessing the code makes it Rt2MI and RtMI the *only* two possible options?


Repository:
  rL LLVM

http://reviews.llvm.org/D14534