[PATCH] D14534: [AArch64] Fix halfword load merging for big-endian targets

[Oliver Stannard via llvm-commits]

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For big-endian targets, when we merge two halfword loads into a word load, the order of the halfwords in the loaded value is reversed compared to little-endian, so the load-store optimiser needs to swap the destination registers.

This does not affect merging of two word loads, as we use ldp, which treats the memory as two separate 32-bit words.

Repository:
  rL LLVM

http://reviews.llvm.org/D14534

Files:
  lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  test/CodeGen/AArch64/arm64-ldr-merge.ll

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