[PATCH] D13644: AVX-512 bit shuffle in 32-bit mode - fixed a bug
Elena Demikhovsky via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 13 04:05:42 PDT 2015
delena updated this revision to Diff 37228.
delena added a comment.
Added a function getConstMaskVector() that creates a proper SDNode for mask.
I checked variable shift on 32-bit mode. I can't say that it is optimal, but correct and does not fail.
The vmovdqa64 instruction is selected instead of vmovdqa32 because the selection is going according to VT.
The final VT of the mask vector is v8i64.
Repository:
rL LLVM
http://reviews.llvm.org/D13644
Files:
../lib/Target/X86/X86ISelLowering.cpp
../test/CodeGen/X86/vector-shuffle-512-v8.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D13644.37228.patch
Type: text/x-patch
Size: 106809 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20151013/e3ce941c/attachment.bin>
More information about the llvm-commits
mailing list