[PATCH] D13644: AVX-512 bit shuffle in 32-bit mode - fixed a bug

[Simon Pilgrim via llvm-commits]

RKSimon added inline comments.

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Comment at: ../lib/Target/X86/X86ISelLowering.cpp:10746
@@ -10729,2 +10745,3 @@
+    MaskNode = DAG.getNode(ISD::BITCAST, DL, TargetMaskVT, MaskNode);
   if (isSingleInputShuffleMask(Mask))
     return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
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Is the constant build vector splitting worth putting into a helper function instead of bulking out this function? I haven't actually checked if there is similar code anywhere else (possibly vector variable shifts?)

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Comment at: ../test/CodeGen/X86/vector-shuffle-512-v8.ll:2
@@ -3,1 +1,3 @@
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F
+; RUN: llc < %s -mcpu=x86-64 -mtriple=i386-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F-32
 
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You are setting a 64-bit cpu and then overriding with a 32-bit triple? Most of the vector shuffle test files are just using triples.

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Comment at: ../test/CodeGen/X86/vector-shuffle-512-v8.ll:29
@@ +28,3 @@
+; AVX512F-32:       # BB#0:
+; AVX512F-32-NEXT:    vmovdqa64 {{.*#+}} zmm1 = [0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0]
+; AVX512F-32-NEXT:    vpermpd %zmm0, %zmm1, %zmm0
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Should this be vmovdqa32?


Repository:
  rL LLVM

http://reviews.llvm.org/D13644