[PATCH] Change order of tablegen generated fastisel instruction code to be based on instruction complexity

[Bill Seurer]

>>! In D6220#4, @wschmidt wrote:
> I like this approach.  What did you do to verify the code that's produced for various targets?  (You probably told me this but I've forgotten.)

I went through some of the generated fastisel .inc files comparing them to a version generated without this change to see if anything stood out as broken.  The ordering is different of course but I am not familiar with the other targets and so I don't know if they are OK or not.  For Power it was all OK.

I tried to build the X86 target on my laptop to run tests there but I never got it to work.

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Comment at: /home/seurer/llvm/llvm-oneoff/utils/TableGen/FastISelEmitter.cpp:747
@@ -722,3 +746,3 @@
           const PredMap &PM = RM.begin()->second;
-          bool HasPred = false;
+          bool OneHadNoPredicate = false;
 
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wschmidt wrote:
> You didn't introduce the problem, but there's a pretty large factoring opportunity between the code below and the sequence starting at 651.  It would be nice to clean that up as long as you're in here.
Yeah, I noticed that those two sections of code were the same.

http://reviews.llvm.org/D6220