[PATCH] Change order of tablegen generated fastisel instruction code to be based on instruction complexity
Bill Schmidt
wschmidt at linux.vnet.ibm.com
Tue Nov 11 13:35:03 PST 2014
I like this approach. What did you do to verify the code that's produced for various targets? (You probably told me this but I've forgotten.)
================
Comment at: /home/seurer/llvm/llvm-oneoff/utils/TableGen/FastISelEmitter.cpp:747
@@ -722,3 +746,3 @@
const PredMap &PM = RM.begin()->second;
- bool HasPred = false;
+ bool OneHadNoPredicate = false;
----------------
You didn't introduce the problem, but there's a pretty large factoring opportunity between the code below and the sequence starting at 651. It would be nice to clean that up as long as you're in here.
http://reviews.llvm.org/D6220
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