[PATCH] Change order of tablegen generated fastisel instruction code to be based on instruction complexity

[Bill Seurer]

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Comment at: /home/seurer/llvm/llvm-oneoff/utils/TableGen/FastISelEmitter.cpp:669
@@ -646,1 +668,3 @@
+                               "  predicate: " + PredicateCheck);
+                }
                 OS << "  if (" + PredicateCheck + ") {\n";
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Should this PrintWarning be an PrintError or an assert?  The X86 target actually hits this at least once so perhaps there is some problem there.

http://reviews.llvm.org/D6220