[R600/SI] Merge const_load for SI

[Vincent Lejeune]

Hi,

these two patches enable merging several S_LOAD_BUFFER_DWORD into a vector instruction.
It does not use the SLPVectorizer because it doesnt seem to work on overloaded intrinsics.


I used codeXL output from AMD's openCL sample "ConstantBandwidth", and it looks like the driver does not attempt to merge more than 4x dword together,
that's why the new pass does not attempt to merge more than 4 scalar load together. I suspect the latency advantage of using a 8 or 16x dword load doesn't outweight
the additionnal scalar register consumption.

Vincent
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