[llvm] r206799 - ARM64: Improve diagnostics for malformed reg+reg addressing mode.
Jim Grosbach
grosbach at apple.com
Mon Apr 21 14:45:57 PDT 2014
Author: grosbach
Date: Mon Apr 21 16:45:57 2014
New Revision: 206799
URL: http://llvm.org/viewvc/llvm-project?rev=206799&view=rev
Log:
ARM64: Improve diagnostics for malformed reg+reg addressing mode.
Make sure only general purpose registers are valid for offset regs and
that 32-bit regs are only valid for sxtw and uxtw extends.
Modified:
llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
llvm/trunk/test/MC/ARM64/diags.s
Modified: llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp?rev=206799&r1=206798&r2=206799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp Mon Apr 21 16:45:57 2014
@@ -1416,7 +1416,7 @@ public:
assert(N == 3 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
+ Inst.addOperand(MCOperand::CreateReg(getXRegFromWReg(Mem.OffsetRegNum)));
unsigned ExtendImm = ARM64_AM::getMemExtendImm(Mem.ExtType, DoShift);
Inst.addOperand(MCOperand::CreateImm(ExtendImm));
}
@@ -2894,6 +2894,17 @@ bool ARM64AsmParser::parseMemory(Operand
Parser.Lex(); // Eat the extend op.
+ // A 32-bit offset register is only valid for [SU]/XTW extend
+ // operators.
+ if (isGPR32Register(Reg2)) {
+ if (ExtOp != ARM64_AM::UXTW &&
+ ExtOp != ARM64_AM::SXTW)
+ return Error(ExtLoc, "32-bit general purpose offset register "
+ "requires sxtw or uxtw extend");
+ } else if (!isGPR64Register(Reg2))
+ return Error(OffsetLoc,
+ "64-bit general purpose offset register expected");
+
bool Hash = getLexer().is(AsmToken::Hash);
if (getLexer().is(AsmToken::RBrac)) {
// No immediate operand.
Modified: llvm/trunk/test/MC/ARM64/diags.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/diags.s?rev=206799&r1=206798&r2=206799&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/diags.s (original)
+++ llvm/trunk/test/MC/ARM64/diags.s Mon Apr 21 16:45:57 2014
@@ -74,6 +74,18 @@ foo:
; CHECK-ERRORS: ^
+; Check that register offset addressing modes only accept 32-bit offset
+; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
+; register.
+ str d1, [x3, w3, sxtx #3]
+ ldr s1, [x3, d3, sxtx #2]
+
+; CHECK-ERRORS: 32-bit general purpose offset register requires sxtw or uxtw extend
+; CHECK-ERRORS: str d1, [x3, w3, sxtx #3]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: 64-bit general purpose offset register expected
+; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2]
+; CHECK-ERRORS: ^
; Shift immediates range checking.
sqrshrn b4, h9, #10
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