[PATCH] [AArch64] Add support for TargetTransformInfo Analysis.

[Chandler Carruth]

LGTM with one question:

+  unsigned getRegisterBitWidth(bool Vector) const {
+    if (Vector) {
+      if (ST->hasNEON())
+        return 128;
+      return 0;
+    }
+    return 32;

Hmm, AArch64 has 32-bit width general purpose registers?


On Wed, Feb 19, 2014 at 11:57 AM, Chad Rosier <mcrosier at codeaurora.org>wrote:

> All,
> The attached patch adds the TargetTransformInfo analysis pass in the
> AArch64 backend.  We hope to continue better defining the APIs as we move
> forward.
>
>  Regards,
>   Chad
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
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