[PATCH] [AArch64] Add support for TargetTransformInfo Analysis.

[Chad Rosier]

> LGTM with one question:
>
> +  unsigned getRegisterBitWidth(bool Vector) const {
> +    if (Vector) {
> +      if (ST->hasNEON())
> +        return 128;
> +      return 0;
> +    }
> +    return 32;
>
> Hmm, AArch64 has 32-bit width general purpose registers?

Yup, and 64.. ;)  Currently, this API is used exclusively by the loop
vectorizer to ask for the width of a vector register.  I'll return 64 in
the scalar case, but this has no functional change as far as I can tell. 
However, I do believe it would be the expected result.  Thanks, Chandler.

 Chad

>
>
> On Wed, Feb 19, 2014 at 11:57 AM, Chad Rosier
> <mcrosier at codeaurora.org>wrote:
>
>> All,
>> The attached patch adds the TargetTransformInfo analysis pass in the
>> AArch64 backend.  We hope to continue better defining the APIs as we
>> move
>> forward.
>>
>>  Regards,
>>   Chad
>>
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>>
>


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