[PATCH] [AArch64]Add support for spilling FPR8/FPR16 registers

[Tim Northover]

Hi Hao,

> There is no test case, as it is too large (hundreds of lines) and difficult to be simplified. There must be many lines of code to achieve a high register presure. But such large test case is useless. As the situation is similar to FPR32, I think the solution is correct.

I've had great success with volatile loads/stores in situations like
this. It forces the allocator to keep the value live until it's
needed. In this case, for example, I think this would work:

%bigtype = type [20 x <1 x i8>]
define void @foo(%bigtype* %addr) {
  %val1 = load volatile %bigtype* %addr
  %val2 = load volatile %bigtype* %addr
  store volatile %bigtype %val1, %bigtype* %addr
  store volatile %bigtype %val2, %bigtype* %addr
  ret void
}

Cheers.

Tim.