[PATCH] [AArch64]Add support for spilling FPR8/FPR16 registers

[Hao Liu]

Hi t.p.northover,

Hi Tim and reviewers,

This patch solves the problems that can't spill FPR8/FPR8 registers in storeRegToAtackSlot and loadRegFromStackSlot.

There is no test case, as it is too large (hundreds of lines) and difficult to be simplified. There must be many lines of code to achieve a high register presure. But such large test case is useless. As the situation is similar to FPR32, I think the solution is correct.

Review, please.

Thanks,
-Hao

http://llvm-reviews.chandlerc.com/D2734

Files:
  lib/Target/AArch64/AArch64InstrInfo.cpp

Index: lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.cpp
+++ lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -487,6 +487,10 @@
     default:
       llvm_unreachable("Unknown size for regclass");
     }
+  } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
+    StoreOp = AArch64::LSFP8_STR;
+  } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
+    StoreOp = AArch64::LSFP16_STR;
   } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
              RC->hasType(MVT::f128)) {
     switch (RC->getSize()) {
@@ -553,6 +557,10 @@
     default:
       llvm_unreachable("Unknown size for regclass");
     }
+  } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
+    LoadOp = AArch64::LSFP8_LDR;
+  } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
+    LoadOp = AArch64::LSFP16_LDR;
   } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
              RC->hasType(MVT::f128)) {
     switch (RC->getSize()) {
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