[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Weiming Zhao]

What I mean is, if you give a inline asm “ldrd %0, [%1]”, both gcc and LLVM
will naturally output “ldrd rx, [rt]”, and LLVM will make rx as a even GPR.
Afterwards, it relies on some specific assembler (e.g. GAS) to consume it.

 

And if you give a well-formed inline asm “ldrd %0, %H0, [%1]”, LLVM will
emit ldrd r_even, r_even+1, 


 

So I think we’re good. Maybe we don’t need a test case for “ldrd rx, [rt]”
because it’s not a guaranteed use case.

 

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation

 

From: Jim Grosbach [mailto:grosbach at apple.com] 
Sent: Wednesday, March 27, 2013 3:40 PM
To: weimingz at codeaurora.org; Zhao
Cc: Måns Rullgård; Renato Golin; Kristof Beyls; Eric Christopher; Jakob
Stoklund Olesen; LLVM Commits
Subject: Re: [LLVMdev] Problems with 64-bit register operands of inline asm
on ARM

 

 

On Mar 27, 2013, at 2:38 PM, Weiming Zhao <weimingz at codeaurora.org> wrote:





Hi Måns

Oh, so you mean GAS will implicitly add a reg even if only one reg is
specified in assembly. Right?

 

Both registers are required in the syntax. GAS is more lenient, but is in
error. We don't need to follow their bad example here.

 

-Jim

 





So llvm's job is to emit an even reg in this case. 
If so, we're good now:
...
            @APP
            ldrd r2, [r1]
            @NO_APP
...

I just need to update the unit test to include this test.

Weiming

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation

-----Original Message-----
From: Måns Rullgård [mailto:mans at mansr.com] 
Sent: Wednesday, March 27, 2013 10:14 AM
To: weimingz at codeaurora.org
Cc: 'Renato Golin'; 'Kristof Beyls'; 'Eric Christopher'; 'Måns Rullgård';
'Jim Grosbach'; 'Jakob Stoklund Olesen'; 'LLVM Commits'
Subject: Re: [LLVMdev] Problems with 64-bit register operands of inline asm
on ARM

"Weiming Zhao" <weimingz at codeaurora.org> writes:




Hi Renato,

GCC doesn’t do this correctly:

#APP

@ 4 "ldrd1.c" 1

               ldrd r4, [r1]

@ 0 "" 2


That is correct in some sense.  The GNU assembler allows a single register
with ldrd and friends, the second one in this case being implicitly one
higher (as in the ARM instruction encoding).

To be maximally compatible, the integrated assembler would need to support
this abbreviated syntax as well.

--
Måns Rullgård
mans at mansr.com

 

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