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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>What I mean is, if you give a inline asm “ldrd %0, [%1]”, both gcc and LLVM will naturally output “ldrd rx, [rt]”, and LLVM will make rx as a even GPR. Afterwards, it relies on some specific assembler (e.g. GAS) to consume it.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>And if you give a well-formed inline asm “ldrd %0, %H0, [%1]”, LLVM will emit ldrd r_even, r_even+1, …<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>So I think we’re good. Maybe we don’t need a test case for “ldrd rx, [rt]” because it’s not a guaranteed use case.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p></o:p></span></p></div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Jim Grosbach [mailto:grosbach@apple.com] <br><b>Sent:</b> Wednesday, March 27, 2013 3:40 PM<br><b>To:</b> weimingz@codeaurora.org; Zhao<br><b>Cc:</b> Måns Rullgård; Renato Golin; Kristof Beyls; Eric Christopher; Jakob Stoklund Olesen; LLVM Commits<br><b>Subject:</b> Re: [LLVMdev] Problems with 64-bit register operands of inline asm on ARM<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal>On Mar 27, 2013, at 2:38 PM, Weiming Zhao <<a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><p class=MsoNormal>Hi Måns<br><br>Oh, so you mean GAS will implicitly add a reg even if only one reg is specified in assembly. Right?<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Both registers are required in the syntax. GAS is more lenient, but is in error. We don't need to follow their bad example here.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>-Jim<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><p class=MsoNormal>So llvm's job is to emit an even reg in this case.<span class=apple-converted-space> </span><br>If so, we're good now:<br>...<br><span class=apple-tab-span> </span>@APP<br><span class=apple-tab-span> </span>ldrd r2, [r1]<br><span class=apple-tab-span> </span>@NO_APP<br>...<br><br>I just need to update the unit test to include this test.<br><br>Weiming<br><br>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<br><br>-----Original Message-----<br>From: Måns Rullgård [<a href="mailto:mans@mansr.com">mailto:mans@mansr.com</a>]<span class=apple-converted-space> </span><br>Sent: Wednesday, March 27, 2013 10:14 AM<br>To: <a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a><br>Cc: 'Renato Golin'; 'Kristof Beyls'; 'Eric Christopher'; 'Måns Rullgård'; 'Jim Grosbach'; 'Jakob Stoklund Olesen'; 'LLVM Commits'<br>Subject: Re: [LLVMdev] Problems with 64-bit register operands of inline asm on ARM<br><br>"Weiming Zhao" <<a href="mailto:weimingz@codeaurora.org">weimingz@codeaurora.org</a>> writes:<br><br><br><o:p></o:p></p><p class=MsoNormal>Hi Renato,<br><br>GCC doesn’t do this correctly:<br><br>#APP<br><br>@ 4 "ldrd1.c" 1<br><br> ldrd r4, [r1]<br><br>@ 0 "" 2<o:p></o:p></p><p class=MsoNormal><br>That is correct in some sense. The GNU assembler allows a single register with ldrd and friends, the second one in this case being implicitly one higher (as in the ARM instruction encoding).<br><br>To be maximally compatible, the integrated assembler would need to support this abbreviated syntax as well.<br><br>--<br>Måns Rullgård<br><a href="mailto:mans@mansr.com">mans@mansr.com</a><o:p></o:p></p></div></div><p class=MsoNormal><o:p> </o:p></p></div></body></html>